Defense Event

Algorithm/Architecture Co-Design for Low-Power Neuromorphic Computing

Nan Zheng

Wednesday, December 13, 2017
3:00pm - 5:00pm
3725 Bob and Betty Beyster Building

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About the Event

Abstract: To satisfy the ever-increasing demands for computing power, neuromorphic computing has emerged as an attractive alternative to conventional computing. This dissertation focuses on developing learning algorithms, hardware architectures, circuit components, and design methodologies for low-power neuromorphic computing that can be employed in various energy-constrained applications. A top-down approach is adopted in this research. Starting from the algorithm-architecture co-design, a hardware-friendly learning algorithm is developed for spiking neural networks (SNNs). The possibility of estimating gradients from spike timings is explored. An SNN hardware equipped with the proposed on-chip learning algorithm is implemented in CMOS technology. Two unique features of SNNs, the event-driven computation and the inferring with a progressive precision, are leveraged to reduce the energy consumption. In addition to the low-power SNN hardware, accelerators for conventional artificial neural networks are also developed to accelerate the adaptive dynamic programing algorithm. The data-level parallelism and the inherent computational patterns in the algorithm are leveraged to improve the energy efficiency of the accelerator. Lastly, an on-chip closed-loop compensation technique as well as a more efficient error correction method are introduced to enhance the degraded reliability of the memory system in a neuromorphic hardware due to the aggressively-scaled supply voltage and integration density.

Additional Information

Sponsor(s): Pinaki Mazumder

Open to: Public